# -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4

PortSystem          1.0
PortGroup           cargo   1.0
PortGroup           github  1.0

github.setup        veryl-lang veryl 0.9.0 veryl-v
github.tarball_from archive
revision            0

description         Veryl\: A Modern Hardware Description Language

long_description    \
    {*}${description}. Veryl is designed as a \"SystemVerilog Alternative\". \
    There are some design concepts: it has a simplified syntax based on \
    SystemVerilog\/Rust, transpiles to SystemVerilog, generates \
    human-readable SystemVerilog code, and comes with integrated tools like a \
    formatter\/linter, and integrates with VSCode.

categories          lang
installs_libs       no
license             {Apache-2 MIT}
maintainers         {gmail.com:herby.gillot @herbygillot} \
                    openmaintainer

fetch.type          git

cargo.offline_cmd

post-fetch {
    system -W ${worksrcpath} "git submodule update --init --recursive"
}

destroot {
    xinstall -m 0755 \
        ${worksrcpath}/target/[cargo.rust_platform]/release/${name} \
        ${worksrcpath}/target/[cargo.rust_platform]/release/${name}-ls \
        ${worksrcpath}/target/[cargo.rust_platform]/release/mdbook-${name} \
        ${destroot}${prefix}/bin/
}